UMC and AP Memory Announce AI/HPC Power-Delivery Collaboration

UMC and AP Memory have begun a technical and manufacturing collaboration focused on power-delivery solutions for AI and HPC systems targeting next-generation data-center requirements.

The partnership combines UMC’s deep trench capacitor (DTC) process and scalable foundry manufacturing with AP Memory’s silicon-capacitor design and system-integration work. The companies intend to move capacitors closer to compute chips, including into interposers or package substrates, to shorten the power-delivery path and improve power integrity.

AP Memory’s DTC-based S-SiCapTM Gen2D discrete silicon capacitor design reached tape-out and initial functional verification in the third quarter of 2026. The next stated step is full-system performance and reliability testing of the capacitors in package substrates.

The companies are also considering extensions to capacitors embedded in silicon interposers and capacitors placed on the backside of package substrates. These approaches remain under development rather than commercially deployed data-center technology.

For data-center operators and AI infrastructure suppliers, the significance is at the server-platform and advanced-packaging layer, not as an announcement of new data-center capacity or energy infrastructure. As AI and HPC loads increase pressure on conventional PCB-level power delivery, successful system qualification could enable denser and more stable power delivery for advanced compute packages.