imec Demonstrates Three-Layer NbTiN Superconducting Circuit Platform for HPC and AI
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imec presented a three-metal-layer NbTiN/a-Si/NbTiN Josephson-junction circuit at the Applied Superconductivity Conference 2026, alongside a three-layer NbTiN interconnect stack. The research demonstration reached junction densities of up to 3.8 million per cm² and 30 nm metal-line widths.
- imec demonstrated a three-metal-layer NbTiN/a-Si/NbTiN Josephson-junction circuit with up to 3.8 million junctions per cm².
- The demonstrated junctions had a minimum diameter of 150 nm; the accompanying NbTiN interconnect used 30 nm metal lines.
- The programme targets CMOS-compatible 12-inch processing, EDA and 2.5D/3D heterogeneous integration.
- The relevance to AI and HPC data centers is strategic and long-term, not an immediate procurement or capacity-development signal.
- No commercial deployment, customer adoption or operational data-center performance was disclosed.
imec has demonstrated a superconducting circuit platform based on NbTiN/a-Si/NbTiN Josephson junctions, using three metal layers and a reported density of up to 3.8 million junctions per cm². The minimum junction diameter in the demonstration was 150 nm.
The Belgian research centre also presented a three-layer, high-density, low-loss NbTiN interconnect stack incorporating conductors and vias. Metal-line width was reduced to 30 nm. imec describes this as roughly a tenfold reduction in feature size versus conventional niobium-based technology.
The programme is directed toward CMOS-compatible 12-inch processing, design and EDA capabilities, and 2.5D/3D heterogeneous integration. imec identifies HPC, AI, quantum-computing control logic, silicon photonics and neuromorphic computing as target application areas, and is focusing the programme on collaboration with fabs, hyperscale data centers and system manufacturers.
For data-center infrastructure, the significance is prospective rather than near-term. If the CMOS-compatible NbTiN platform proves technically and economically scalable, it could broaden the options for reducing compute energy consumption and interconnect losses in AI and HPC systems. The disclosed work does not indicate a commercial product, customer deployment, or operational use in a data center.
imec characterizes major gains in energy efficiency, compute density and bandwidth relative to advanced CMOS as potential advantages of superconducting technology. Those figures should not be interpreted as measured system-level results from the demonstrated circuit.
The work is an early technology signal for potentially lower-energy compute components and interconnects in future HPC and AI infrastructure. It remains a research-platform demonstration rather than a commercial data-center technology or evidence of system-level performance in operation.
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